Technical Field
The present disclosure relates to three dimensional (3D) stacked memory devices, and more particularly, to 3D stacked package-on-package memory devices with copper pillars electrically interconnecting the package units thereof.
Description of Related Art
Three dimensional package-on-package (PoP) technologies for logic device plus memory stacks include an integrated circuit packaging to vertically combine a logic device or a memory controller and a memory package stack which contain high capacity or combination memory devices. The memory package stack includes two or more packages which are installed atop each other with direct vertical chip connection using through silicon via (TSV) to route signals therebetween. This allows higher performance and component density in handheld devices, such as mobile phones, personal digital assistants (PDA), and digital cameras.
In general, cost for 3D DRAM packages increases by using expensive TSV staking. TSV technologies utilizing vertical vias in the silicon wafers are used to interconnect each of the chips. Using through silicon vias substantially results in shortened interconnect length, improved electrical performance, and reduced power consumption by the memory device.
Alternatively, 3D memory stack with copper pillar interconnections uses solder bumps with plating a lead-free solder cap on top of the copper pillar. Requirements for developing 3D stack with copper pillar interconnections lead to new package technologies, particularly replacing wire bonding in many higher end devices that require high I/O density, low production cost and small area packaging.